1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory composed of single-transistor memory cells.
2. Description of Related Art
At present, semiconductor memories composed of single-transistor memory cells each consisting of one transistor and an associated capacitor for forming one information storing unit, have been the most widely utilized. In this type of semiconductor memory, if a transistor and an associated capacitor are formed in the same plane, the size of one memory cell becomes too large. Therefore, in order to miniaturize the memory cells so as to increase the density of the semiconductor memory, a so called stacked memory cell has been proposed and reduced to practice. In the stacked memory cell, an electric charge storage capacitor is formed by stacking two or more conducting layers in such a manner that an insulating film is sandwiched between each pair of adjacent conducting layers.
In order to further miniaturize the stacked memory cells, it has been an ordinary practice to make the insulating layer of the stacked capacitor as thin as possible with the intention of preventing a capacitance decrease of the memory cell caused by a decrease in area of the capacitor. However, the thinning of the insulating layer of the stacked capacitor has resulted in increased numbers of pin holes and a decrease in the voltage that can be withstood, and therefore, in a decrease in reliability.